Pin counts are exploding. Devices with 4000-8000+ pins are now common offerings of the large FPGA and Network IC vendors. How do you plan to build schematic symbols for such a behemoth?

Bill OLearyFebruary 1, 2019PartBuilder

FPGA-PHYSICAL vs FPGA-LOGICAL Part Builder Flows

Before the CadEnhance PartBuilder tool was created, the creation of complex multi-section FPGA symbols was quite a chore, and usually fell to a collaboration between the Board Engineer and the Part Librarian.

Bill OLearyJanuary 3, 2019PartBuilder

How can I automate the creation of schematic symbols for Xilinx, Intel, Lattice and MicroChip FPGAS?

Here we examine the process used to create a high Pin Count device from Xilinx part Data using the CadEnhance Part Builder Tool. The Part Builder tool is designed to get accurate pin information from a variety of sources.

Blog