How can I automate the creation of schematic symbols for Xilinx, Intel, Lattice and MicroChip FPGAS?
This short video shows how PartBuilder creates schematic symbols for FPGA devices using the FPGA_PHYSICAL flow for a 484 pin Xilinx Artix7 FPGA in less than 15 minutes. In fact, PartBuilder can build symbols for Any Size FPGA from AMD/Xilinx, Intel/Altera, Lattice and MicroChip in less than one hour.
This is how we do it:
PinExtract instantly reads the detailed Packaged File for the device It extracts all relevant pin information including Pin Bank numbers, Bank Types, and Pin Delay specs.
In the AMD/Xilinx case, the Package file is created using the Vivado ‘write_csv’ function for the selected FPGA.
Smart-Frac understands the banking and power structure of the FPGA devices and creates the Symbol Description Language (SDL) file to describe a set of symbols split into one symbol per generic I/O bank and one for each transceiver I/O bank. It creates a symbol for the configuration pins and as many symbols as needed to fit all the power pins.
If needed, the user can use the SDL-EDITOR to modify the SDL and rearrange/optimize the bank to symbol pin layouts for their application
SDL-Mapper reads the SDL file and builds an internal database mapping all the device pins to the symbols defined in the SDL file
Symbol-Builder uses the internal symbol database to create the Actual symbol files for the selected Cadence DE-HDL and Capture, Mentor dxDesigner and Pads, Altium, and Zuken CR-8000 Schematic Tools
Part Builder supports 2 Flows for building FPGAS
FPGA_PHYSICAL: Build generic symbols for the part using the FPGA physical/bank pin names. The fractured into multiple symbols (typically one symbol for one or 2 I/O Banks.)
FPGA_LOGICAL: Build a custom part for each FPGA design. The majority of symbols are organized by function instead of by bank, using actual design pin names. The Vendors package Pin-Names are added for unused pins, special function pins and Power Pins
For large complex FPGA designs, cadEnhance recommends using the FPGA_LOGICAL option and this blog post describes the benefits in more detail
