FPGA Pin Planner

Manage FPGA Pinouts in your Schematics Logically

Board Design Engineers have long been saddled with the unenviable task of connecting Programmable Logic Devices in their schematics while keeping track of Pinouts and Pinout Changes as the design evolves.

FpgaPinPlanner works in concert with PartBuilder to remove the pain points from these tasks.

FPGA Pin Planner Highlights

1. Supports Altera/Intel, Lattice Semiconductor, Microchip/MicroSemi and Xilinx FPGA and CPLD devices

2. Create Initial FPGA pinouts from skeleton HDL code and a mix of guide files

   1. Guide Files can be

      1. Placement Constraint Files created by the vendor

      2. PinReport files created by vendor from an existing FPGA design.

      3. PinPlanner PinOrder files which directs the tool to place matching pins in matching banks.

3. Enables easy migration of existing designs into new FPGA devices, either into new families or larger or smaller devices in the same family.

4. Creates the Required Pin Constraint file with pin placements and IO standard and configurations for the Selected FPGA Device

   1. User can include efficient pragmas in the HDL to declare IO standards and configs like Pullups/Keepers

5. Creates the Compiled Pin Report matching the vendor Tools syntax for the FPGA

6. Works with PartBuilder to create the LOGICAL FPGA symbols with all of their advantages in a schematic design

7. Keeps FPGA devices in Sync with PCB pin Swapping

   1. Reads Pin Swap Reports from the PCB design tool

      1. Check out the dal swap tool from dalTools for an ultra-efficient means to swap your pins in Allegro PCB.

   2. Provides pin-swaps back to FPGA tools using the FPGA vendors contraint files

      1. FPGA designer verifies that all PinSwaps are legal by rerunning FPGA compiler with updated pinout

   3. Provides pin-swaps back to PartBuilder with updated Compiled Pin Report.

A little History

Our first board design at a High Performance Computing startup required 16 large FPGAS to perform the compute and memory functions, and required 5 smaller FPGAs to manage and configure the larger devices. We knew from the start that the FPGA selection and partioning of functions between the devices would be very fluid. We also knew that we would need to swap most of the FPGA Pins at the board level to have a chance at routing the board on the 24 layer PCB stackup we came up with.

At the time, most FPGA schematic symbols were drawn split into individudal FPGA Banks, using the vendors generic physical pin name for each pin. The Hardware designer was required to add the symbols for each physical bank, and then manually add wires with the proper name using the Vendor’s post-compile FPGA pin report as a guide. We now call this flow the FPGA PHYSICAL FLOW

With 16 FPGAs, we didn’t even have the Vendor’s Pin Reports yet, and we couldn’t wait the six months it might take to get the intial design through them, so there was no way this was going to work.

This odious task was actually the genesis of the CadEnhance product line.

To solve the problem we created and used what we now call our FPGA LOGICAL FLOW. We created skeleton Verilog files defining the pins for each FPGA design, and then we built an internal Pin Planner tool to build Initial Pinout Reports for the each of the devices. These reports matched the syntax and formats of the FPGA vendor’s actual Pin Reports. The Pin Planner tool also produced a constriaint File for the FPGA vendor tool to provide the intial pinout starting point so that the FPGA tool and symbols were in sync.

We used a very early verison of PartBuilder to create ASIC like symbols for each FPGA from the early Pin Reports, where pinNames were taken from the actual FPGA design, and the Symbols were split into Logically grouped functions instead of Physical Banks. Now that we had Schematic Symbols for each FPGA with logical pinNames, we were able to proceed with the schematic design six months earlier than if we had waited for the actual pinout results. It was also so much easier to connect the symbols and check the schematic because we were using the logical pinNames.

The LOGICAL flow allowed us to use PartBuilder tool to re-create the symbols from the updated Pin Reports, when the real pinout files were avaialable with very low effort. Instead of having to rewire the whole FPGA design, we could simply update the symbols in the schematic whenever the pinout(s) changed.

To solve the pinSwapping issue, we enabled PartBuilder to add PIN_SWAP codes to select groups of pins in the symbol under the joint guidance of the board engineer and the FPGA designer. The swap codes allowed the PCB designer to safely swap the FPGA pins in the PCB tool to improve or even achieve routability. We added functionality to the PinPlanner tool so it could read the Pin Swaps from the PCB Tool, and update the FPGA Pin Constraint File in order to keep the FPGA pinout in sync with the board. The FPGA tool then verifies that the swapped pinout is still valid and produces the final Compiled Pin Report File which PartBuilder uses to update the Symbols with the new pinout to re-sync the schematic and the board.