FPGA-PHYSICAL vs FPGA-LOGICAL Part Builder Flows
Before the PartBuilder, creating complex multi-section FPGA symbols was quite a chore. The task usually fell to a collaboration between the Hardware (HW) Design Engineer and the Part Librarian. Since resources dedicated to Schematic symbol creation were limited, only one set of schematic symbols was usually built for an FPGA device. The pins were drawn using the dedicated FPGA pin names, and they were usually broken up into the separate I/O banks or pairs of I/O Banks. This is what CadEnhance refers to as the FPGA-PHYSICAL flow because the FPGA is drawn as a representation of its physical layout.
The FPGA PHYSICAL FLOW
CadEnhance PartBuilder and it’s Symbol Description Language (SDL) enables the FPGA-PHYSICAL flow by extracting all pin data from the selected vendor’s FPGA package file. PartBuilder’s Smart-Frac feature uses its knowledge of FPGA bank partitions to create the initial SDL File to describe a customizable set of symbols fractured into Dedicated Functional banks, Generic IO banks, XCVR Banks and Power Symbols. Using the PartBuilder FPGA-PHYSICAL flow, highly optimized schematic symbols for any size FPGA device From AMD/Xilinx, Intel/Altera, Lattice and MicroChip/Microsemi can be built in under an hour using the PHYSICAL flow. In fact an initial set of functional symbols is created in less than 5 minutes.. The rest of the time is spent optimizing the symbols for the customers application.
You can see more about this in BuildingHighPinCountDevices blog-post.
DDR4 Interface Schematic Drawn using FPGA Symbols created with FPGA_PHYSICAL Flow. Notice how the Connection Names are completely unrelated to the Symbol Pin Name. The Designer is forced to lookup the Connection Name for each symbol pin in an FPGA pin Report in order to make the connections. This can take hours to days for a large design and there is no way to verify the connections visually without using the same interactive lookup process.
Lets say a company uses the Xilinx Spartan-6 Device XC6SLX16-2FTG256 which is a 256 PIN BGA with 186 User I/O in their preferred part list. In one application the device might be used as a FLASH controller with an interface to a PowerPC-Host, while in another application the same device might be used as a DDR3 memory controller with another FPGA as the host.
While the part is physically exactly the same, the pin usage and connections for the 2 parts are completely different.
If there is only one schematic representation of the part, it is up to the design engineer to make the proper connections between the FPGA and the other memories, other FPGAs and micro-controllers it is connecting to. This requires the engineer to interactively connect wires with the proper names to the proper pins of the device, which can become a very tedious manual process.
When you look at the newer FPGAs on the market today with over 2000 pins, the problem grows even more daunting.
Now lets say the FPGA design engineer tells the HW design engineer (if they are different people), that the planned pinout was rejected by the FPGA compile tool or that some changes had to be made to move one pin to a special clock pin, which caused all the other pins in an IO bank to move. The HW engineer now has to go back and manually reconnect all the signals around in the schematic to correct the pinout.
Its good to know that the CadEnhance CE-HDL Tool comes to the rescue for Cadence Allegro-HDL users. CE-HDL automates the task of connecting the FPGA pins, using the final FPGA vendor’s pin report as a guide.
Is There a better way?
Enter the CadEnhance FPGA-LOGICAL Flow from PartBuilder. In this flow, a new set of symbols is created for each design application using the same physical FPGA. So PartBuilder is used to create one set of schematic symbols for the FLASH Controller FPGA, and a completely different set of symbols drawn for the DDR3 MEMORY Controller FPGA.
Because PartBuilder is doing the difficult job of reading the pin information, the design engineer or librarian now just have to decide what pins they want to show on what symbols. They do that with the Symbol Description Language (SDL) File. The Pin information is read directly by PartBuilder from the compilation report for each design. The SDL file controls the display and location of the logical pin names on each symbol.
Now the symbols can be broken apart into much more meaningful blocks. For the FLASH controller FPGA, there would be a symbol all the pins related to the PowerPC host in the first design, and another one with all the FLASH interface pins. In the DDR3 Controller case, there might be one or 2 symbols to define the DDR3 Memory interface, and one symbol for the connection to the other FPGA.
The 2 sets of symbols would share the same layout for the Core Power, Ground, I/O Power and Configuration Blocks, so large portions of the SDL file can be directly re-used between the 2 design with SDL Include files.
The Same FPGA DDR4 Controller Schematic and connections drawn using FPGA_LOGICAL Flow. Notice how the Connection Names and the symbol Pin Names and are Directly related. It is easy to verify connections visually
When the designer goes to connect the pins in the FPGA_LOGICAL flow, the pin names on the symbol match the wire names, so the designer no longer needs to cross-check the FPGA report to see what wire connects where. With our CE-HDL Tool the wires can be automatically added from the pinNames on the symbol, reducing the likely hood of improper connections even further.
Furthermore, if the FPGA pinout needs to be tweaked, or even completely overhauled, PartBuilder can be run with the same SDL file and the newly compiled pin report, and then the symbols in the schematic just need to be refreshed. The pins will magically move to the proper locations.
With that in mind, PartBuilder can also add pin-swapping controls into the generated symbols, which gives Allegro PCB the ability to swap pins (within enabled groups) on the fly. This can be used to reduce routing congestion and maximize the efficiency of the existing routing layers (and even allow a design to be completed in fewer routing layers). With the FPGA Pins add on tool the swaps can be read back from allegro, fed back to the FPGA design tool and to the symbols at the same time providing an error free means to optimize the FPGA pinout.
Here is a list of the Advantages of using the FPGA_LOGICAL flow in a schematic design:
This Table summarizes the benefits of using Symbols drawn with the FPGA Logical vs the FPGA Physical Flow in your schematics and Board Designs
Click on the Video below to see a slide show comparing the benefits of the 2 flows
CadEnhance is excited to report the development of a new technology that works within the Allegro toolset called “virtual swap gates” which allows the designer to swap whole functions between banks of an FPGA on the fly. The new technology will be enabled with the release of the CadEnhance Packager Assistant tool.
Summary
Given a choice between the 2 flows, and taking into account the advantages described above, CadEnhance would always recommend using the FPGA_LOGICAL flow. That said, PartBuilder completely supports the FPGA_PHYSICAL flow, and provides great accuracy and efficiency boosts in creating the symbol set. Note that the CadEnhance CE-HDL Tool is provided to support AllegroHDL users by magically making connections to their FPGAS if they were created using the FPGA PHYSICAL flow