How can I automate the creation of schematic symbols for Xilinx, Intel, Lattice and MicroChip FPGAS?

Here we examine the process used to create a high Pin Count device from Xilinx part Data using the CadEnhance Part Builder Tool. The Part Builder tool is designed to get accurate pin information from a variety of sources.

Bill OLearyJanuary 1, 2019PartBuilder, Xilinx, AMD/Xilinx, Altera, Intel/Altera, Lattice, Cadence, AllegroHDL, DE-HDL, Capture, Capture-CIS, Orcad, Altium Designer, Zuken CR-8000, automation, schematic Symbols

Blog